1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, to a device in which there is effected a technique applied to a dynamic type RAM (random access memory) containing a voltage inversion circuit, for example.
2. Description of the Prior Art
As miniaturizations of circuit elements have made advances with high integration and mass storage, a method to reduce the working value of an internal supply voltage in a chip to e.g., approximately +3.3 V has been adopted as one means in compensating for the reduction of dielectric strength. Regarding this since it is highly effective to standardize and unify an external supply voltage, fed from the outside, for example, +5.0 V, a dynamic type RAM, etc., is provided with a voltage conversion circuit for forming the voltage of the above-mentioned internal power supply to be stabilized, i.e. by reducing voltages of the external supply voltage.
On the other hand, among the above-mentioned dynamic RAM etc., for example, in order to be able to detect early a MOSFET (metal oxide semiconductor field effect transistor, in this specification, MOSFET is a general designation for insulated gate type field effect transistor) which is likely to cause interference due to, for example, defects of a gate oxide film, a so-called burn-in (aging) test is carried out performing an acceleration test with the power supply voltage and ambient temperature abnormally raised. At this time, the value of the internal power supply voltage is raised immediately before a normal circuit element becomes destroyed, and an error detection ratio and test efficiency will be raised.
Known dynamic type RAMs containing a voltage conversion circuit are described in Japanese patent application laid-open No. 110225/1984 etc. Also, known voltage conversion circuits (e.g., voltages limiter circuit or voltage reducing circuit) for producing an internal supply voltage from an external supply voltage are discussed in the following Japanese unexamined patent applications:
patent application laid-open No. 111514/1984 and PA1 patent application laid-open No. 185461/1989
These patent applications also make reference to an aging (burn-in) test of a semiconductor device. That is to say, the dependency of the internal power supply voltage on the external power supply voltage is made smaller in the normal operation whereas the dependency is made larger at the time of aging test. Therefore the operation of the circuit operating with the internal power supply voltage as a power source becomes stable at the time of normal operation, and at the time of the aging test a sufficiently higher voltage than that of the normal operation is applied.
With respect to the above-mentioned prior art, the accuracy of the internal power supply voltage with the aging of the semiconductor device has not been considered sufficiently.
In addition, the standard voltage generating circuit is described in the IEEE Journal of Solid-State Circuits, Vol. SC-15, No.3, pp. 264-269, June 1980 and Japanese patent application laid-open No. 296491/1989.